Dr. Ryan Kastner, University of California
Reconfigurable Hardware Security
Sp-421 on 11 August 2005, 1500-1550 (Powerpoint)

IReconfigurable hardware has quickly become ubiquitous in embedded computing systems. Reconfigurable devices control our transportation (cars, planes), enable communication (wireless transceivers, network routers), and are even found on other planets (Mars Rover). The power of reconfigurable hardware lies in its unique blend of flexibility and performance. It combines the post-fabrication programmability of software running on a general purpose processor with the spatial computational style employed in hardware designs. Unfortunately, if unprotected, reconfigurable hardware can be exploited to disrupt critical operations, snoop on supposedly secure channels, or even to physically melt the device. Somewhat surprisingly, there is little research on the security aspects of these unique devices.

This talk focuses on security for reconfigurable hardware. Dr. Kastner will start by giving a brief history of reconfigurable hardware, from its roots at UCLA in the 1960s, to its commercial emergence for hardware prototyping in the mid 80s, though its current widespread use in computing systems. Moving through the years, Dr. Kastner highlight architectural features of a variety of reconfigurable devices, with a focus on FPGA architectures. Then, he will discuss the current state-of-the-art methods in securing these devices, specifically methods to secure the bitstream; the data used to program the device. A secure bitstream allows us to safely run different applications on the same piece of hardware, and protect the intellectual property of the applications.

Dr. Ryan Kastner
Ryan is an assistant professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. He received a PhD in Computer Science (2002) at UCLA, a masters degree in engineering (2000) and bachelor degrees (BS) in both electrical engineering and computer engineering (1999), all from Northwestern University. His current research interests lie in the realm of embedded system design, in particular reconfigurable computing, wireless communications and underwater sensor networking.

Professor Kastner has published over 50 technical articles, and is the author of the book, "Synthesis Techniques and Optimizations for Reconfigurable Systems", available from Kluwer Academic Publishing. He is a member of numerous conference technical committees including International Conference on Computer Aided Design (ICCAD), Design Automation Conference (DAC), International Conference on Computer Design (ICCD), Great Lakes Symposium on VLSI (GLSVLSI), the Ethe International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) and the International Symposium on Circuits and Systems (ISCAS). He serves on the editorial board for the Journal of Embedded Computing.